As the level of integration of digital integrated circuits increases, the generation and distribution of internal clock signals becomes more problematic. For example, distributing synchronous clock signals to many registers (e.g. thousands) throughout a very large scale integrated circuit can introduce significant clock skewing due to the parasitic resistive and capacitive loading of the clock signal lines.
One technique for minimizing clock skewing due to mass distribution of a synchronous clock signal is to use a phase lock loop (PLL) whereby a reference clock signal is distributed and used to generate and synchronize many local clock signals. The PLL can also be used to multiply the frequency of the reference clock signal thereby generating local clock signals which are synchronous frequency multiples of the reference clock signal.
Implementing a PLL in a typical digital integrated circuit is undesirable since the typical PLL requires the use of analog circuits, such as a voltage controlled oscillator, phase detector, charge pump, and low pass filter.
Other types of so-called locking loops have been commonly used for generating timing reference signals used in electronic circuits. One example of such a locking loop is a so-called delay lock loop or digital delay lock loop. The operation of exemplary locking circuitry or delay lock loops is described in the following patents, the disclosures of which are incorporated by reference: U.S. Pat. Nos. 5,663,665, 5,771,264, 5,642,082, and 5,744,991.
This invention arose out of concerns associated with providing improved delay lock loops and methods of signal locking, particularly in the area of implementing delay lock loops.